SGP Hardware Notes

Summary Information

Host Memory Use: Usually placed at the upper end of memory (near 4G) by the BIOS.

Host I/O Use: none

Interrupt: One of 3-12, 14 or 15 (sharable between two or more SGP cards).

Links: Link 0 is the upper connector; Link 1 is the lower connector.

RS-232 Cable Specifications
The SGP processor card has two DB15 male connectors. The upper connector is link 0; the lower connector is link 1.

The following table identifies pin connections between DB15 and DB25 connectors.

Note: To retain FCC Class B qualification all cables must be fully shielded and the shielding must be connected to the metal connectors.

Pin Numbers Description Direction
From/To SGP

Female DB15 Male DB25

2 2 TD, Transmit Data FROM

4 3 RD, Receive Data TO

3 4 RTS, Request to Send FROM

10 5 CTS, Clear to Send TO

12 6 DSR, Data Set Ready TO

8 7 GND, Common Signal Ground not applicable

5 8 CD, Carrier Detect TO

13 15 TC, Transmit Clock TO

14 17 RC, Receive Clock TO

1 20 DTR, Data Terminal Ready FROM

15 24 XTC, DTE Clock FROM

Revision 1.1 (January 2002)

Pin Numbers		Description	Direction From/To SGP
Female DB15	Male DB25	Description	Direction From/To SGP
2	2	TD, Transmit Data	FROM
4	3	RD, Receive Data	TO
3	4	RTS, Request to Send	FROM
10	5	CTS, Clear to Send	TO
12	6	DSR, Data Set Ready	TO
8	7	GND, Common Signal Ground	not applicable
5	8	CD, Carrier Detect	TO
13	15	TC, Transmit Clock	TO
14	17	RC, Receive Clock	TO
1	20	DTR, Data Terminal Ready	FROM
15	24	XTC, DTE Clock	FROM